Job Description

Job Title: Low-Latency FPGA Developer – HFT Systems

Location: Chicago, IL (100% Onsite)

Type: Contract

Key Responsibilities:

• Design, implement, and optimize FPGA firmware (VHDL/Verilog) for Xilinx UltraScale+ or Intel Stratix 10 platforms deployed on custom PCIe cards.
• Collaborate with C++ development teams to tightly couple FPGA hardware with low-latency trading applications through PCIe DMA and MMIO.
• Build ultra-low-latency data path logic for market data feed handlers, order entry engines, and real-time risk modules.
• Tune clocking constraints and perform static timing analysis to ensure deterministic execution under sub-10ns latency budgets.
• Develop and simulate firmware using Vivado, Quartus, ModelSim, and Mentor Questa, followed by hardware-in-the-loop testing.
• Optimize and validate PCIe Gen3/Gen4 interfaces, multi-clock domain synchronization, and DMA pipelines.
• Use tools such as logic analyzers, JTAG, and protocol analyzers for real-time hardware debugging.
• Ensure all firmware is compliant with MiFID II, SEC, and Citadel’s internal regulatory standards.
• Maintain accurate technical documentation, test plans, and post-deployment incident reports.

Required Skills & Experience:

• 10+ years of FPGA firmware development in high-frequency trading, telco, or embedded real-time domains.
• Deep expertise in VHDL and/or Verilog, including pipelined architectures and high-throughput data paths.
• Proven experience with Xilinx Vivado and/or Intel Quartus for full project lifecycle (synthesis, place & route, timing closure).
• Strong hands-on experience with PCIe interface design, including Gen3/Gen4 DMA engines, latency optimization, and MMIO communication.
• Must-have: Advanced C++ development skills for low-latency integration with FPGA (drivers, middleware, and real-time applications).
• Excellent debugging skills using hardware emulators, JTAG, logic analyzers, and signal probes.
• Familiarity with high-speed SERDES, clock domain crossing, and FPGA resource optimization.
• Deep understanding of networking protocols (UDP/TCP, Ethernet MAC/PHY, FIX, PTP).
• Degree in Electrical Engineering, Computer Engineering, or similar technical discipline (Master’s preferred).
• Prior experience working in co-location data centers or latency-sensitive HFT environments is highly desirable.
• Exposure to CXL (Compute Express Link) and high-bandwidth memory interfaces (HBM2/3).
• Experience building firmware for tick-to-trade, market replay, or hardware order book acceleration.
• Understanding of multicast feed normalization, timestamping, and cross-asset arbitrage architectures.
• Familiarity with Git, Jenkins, Perforce, and agile/hybrid SDLCs in highly regulated environments.

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